SDxCentral Magazine - Issue 2
7-Eleven networks in Taiwan, Verizon’s CTO, OpenAI's networking, and AMD's head of networking tech
News - Open Networking Standards
The latest news on networking, cloud, and AI infrastructure
Featured
-
Ultra Ethernet Consortium releases Version 1.1 to boost scale-up networking and congestion control
Standard update targets AI network bottlenecks
-
Meta details next-gen AI infra: Custom multiterabit switches & unified fabrics
OCP provides a glimpse at the stack set to power Muse agent workloads
-
Cisco nabs Nvidia for pluggable power up, snuggles closer to SONiC
More power out and less power consumption
-
Meta builds custom 'IceCube' AI network switch using Nvidia's Spectrum-6 ASICs
Switch pairs FBOSS OS with 102T chip for 100K+ GPU clusters
-
Network switches get simple with Meta, Microsoft-backed open standard
OCP introduces OSPA
-
Astera Labs to extend PCIe 7 for copper and optical connections
‘Industry first’ portfolio looks to bridge copper-to-optical divide to drive AI infra scaling
-
Nvidia-backed Upscale unveils fabric that lets engineers break vendor lock-in and mix rival XPUs
Upscale’s Token Fabric to create network bridge for the dream of heterogeneous computing
-
Arista Networks unleashes ESUN-based rack-scale architecture targeting AI infra
Platform was designed with input from a phalanx of industry heavyweights
-
SoftBank demos virtual hyperscaler to rival NTT networking standard
SoftBank's wide-area workload shift tech aims to sate AI compute demand regardless of power bottlenecks
-
TM Forum targets network autonomy rollout with reusable L4 blueprints
Some 40 self-driving packages to launch by next summer
-
Mysterious Chinese silicon firm joins Lenovo, Naddod as SONiC members
Network ASIC developer Zhanwang joins optics vendor and PC giant as general members
-
Nu Quantum CEO on the $15B Q-day networking proposition
Carmen Palacios-Berraquero warns against setting post-quantum network standards too soon
-
JEDEC unveils 'industry first’ silicon photonics standard to drive reliability
Baseline framework looks to light up AI infrastructure adoption
-
Cisco and Nvidia: Quantum networks will be hybrid or bust
And open interopability is key
-
DeepSeek teams up with Huawei to beef up Ascend chip programming tools
Chinese lab taps Microsoft’s TileLang in push for simpler AI programming
-
Broadcom comes out fighting in Nvidia AI networking race
EMEA network chief touts Ethernet lead; lauds OpenAI protocol as networking standard for scale-up and out
-
NTT DoCoMo adds Nokia equipment to boost multivendor O-RAN efforts
Nationwide deployment set to take place after initial fireworks festival trial
-
Verizon stirs Samsung AI-powered sensing tech into 6G sneak peek
The recent trial hinted at what's to come
-
SDxCentral Magazine out now: How 7-Eleven networks Taiwan together
Understand the network behind Taiwan’s own backbone
-
Comcast digitally connects enterprises to the last mile, and Xfinity streaming to the edge
Equinix and Fastly partnerships leverage APIs and edge-based compute for quick installations and uninterrupted football streams
-
Cisco missed the MRC memo, so an engineer built his own multiplane party
Cisco engineer DIYs an MRC emulator
-
AMD brings UCIe connectivity to Versal adaptive chips
Chip giant embraces open chiplet interconnect standards to unlock heterogeneous compute
-
Meta’s custom transport protocol embraces packet chaos to boost AI throughput
MetaRoCE reimagines Ethernet data transfers to fix network latency at AI scale
-
ITU backs Japanese framework for low-latency all-photonic networks
NTT, NEC, and 1Finity-backed effort secured international standard support
-
Kubeflow solidifies enterprise AI role with CNCF graduation
Nine years from debut, Kubeflow hits 260 million downloads
-
Nvidia joins Israeli consortium to develop quantum-secure network technologies
Allot-led coalition looks to PQC and QKD to combat future quantum threats
-
Cerebras unveils low latency AI workload speed demon rack-scale platform
CS-4 promises 30-times faster AI workloads compared to GPU platforms with latency as low as two milliseconds
-
Credo spearheading OCP project to develop open chiplet interconnects
Lightweight Serial Interconnect effort looks to create open options to smash the AI memory wall