SDxCentral Magazine - Issue 2
7-Eleven networks in Taiwan, Verizon’s CTO, OpenAI's networking, and AMD's head of networking tech
News - SmartNICs, DPUs & ASICs
The latest news on networking, cloud, and AI infrastructure
Featured
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Meta details next-gen AI infra: Custom multiterabit switches & unified fabrics
OCP provides a glimpse at the stack set to power Muse agent workloads
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Cisco nabs Nvidia for pluggable power up, snuggles closer to SONiC
More power out and less power consumption
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Nvidia adds Google Falcon support to meet growing transport diversity demands
Falcon swoops in to join MRC
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Meta builds custom 'IceCube' AI network switch using Nvidia's Spectrum-6 ASICs
Switch pairs FBOSS OS with 102T chip for 100K+ GPU clusters
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Nvidia opens up Vera Rubin rack and tray designs to OCP
MGX 1.2 spec doubles down on liquid cooling
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Astera Labs to extend PCIe 7 for copper and optical connections
‘Industry first’ portfolio looks to bridge copper-to-optical divide to drive AI infra scaling
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Mysterious Chinese silicon firm joins Lenovo, Naddod as SONiC members
Network ASIC developer Zhanwang joins optics vendor and PC giant as general members
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Nvidia ropes in 100-strong posse to leash rogue AI agents after OpenAI's walkabout
OpenShell and Sentry to corral the ‘iPhone of tokens’
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Broadcom comes out fighting in Nvidia AI networking race
EMEA network chief touts Ethernet lead; lauds OpenAI protocol as networking standard for scale-up and out
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VMware axes distributed firewalls for smartNICs citing low demand: report
Pivot amid ambitions to focus on VCF efficiency stack
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Meta bakes networking on-chip in custom silicon designed to cut CPU hops
MTIA 300’s house onboard NICs to ditch PCIe bottlenecks
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Meta’s custom transport protocol embraces packet chaos to boost AI throughput
MetaRoCE reimagines Ethernet data transfers to fix network latency at AI scale
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Scale-in? Nvidia’s ‘fifth’ pillar of AI networking rests on shaky ground
Nebulous Hot Chip updates include apparent acceleration for north-south traffic and a multiplane configuration ‘spotlight’
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Nvidia’s low-latency AI inference LPX racks hit full production
Neocloud Nebius among early adopters of platform promising four-times faster responsiveness for AI agents
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NEC taps Cornelis to aid AI and HPC networking in Japan
Successful tests in Europe will see the pair deploy Omni-Path and eventual Ethernet-based platforms
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India’s chip ambitions advance as networking silicon startup marks milestone
Government-backed startup’s Vihaan chip to enter production tape-out in 2027
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AI hyperscale and agentic demands helped Cisco smash revenue records
AI infrastructure push pays off with triple-digit hyperscale order growth
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Marvell targets AI memory woes with inference-boosting Bravera controller
Memory efficiency play sees reveal of photonic fabric to reduce GPU stalls
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Fabless networking startup hits $2.8B valuation to challenge legacy silicon giants
Fidelity, Intel back Xsight to scale its programmable, AI-focused DPUs and switch silicon
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Samsung and Broadcom announce plans to collaborate across memory, foundry, and packaging technologies
Companies estimate the partnership will be worth more than $200 billion by end of decade
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AMD challenges Nvidia’s networking dominance with Helios racks boasting 50% higher bandwidth
Featuring programmable 400G DPUs and a single-hop fabric, Helios targets a streamlined, open-standards approach to rival NVL72
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Nvidia crowned AI networking’s top dog, but its throne isn’t quite safe
Gartner server CPU gong goes to AMD while Marvell outclasses on optical connectivity
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Microsoft to deploy AMD Helios rackscale solution to support inference workloads and Azure services
AMD will start shipping Helios later this year
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Iridium launches resilient GNSS PNT ASIC commercially
The satellite communications provider seeks to protect timekeeping and GPS authentication at critical sites and devices
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Fabless South Korean startup wants to entice European inference chip-hungry enterprises
FuriosaAI rejected an $800 million acquisition bid from Meta to go its own way
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Meta: Recycling memory is magic solution to RAM supply misery
Vistara solution validates CXL standard while keeping rocketing flash prices at the door
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Marvell boosts custom silicon push with AMD engineering lead hire
Engineering lead behind AMD EPYC efforts joins custom XPU team
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DriveNets unveils high-capacity AI fabric platforms to connect thousands of XPUs
Broadcom silicon powers 1.6T offering aiming to reduce network latency for AI workloads