The UALink Consortium published the second generation of its flagship standard.

UALink Common Specification 2.0 debuted a little under a year following the group’s first interconnect spec. The latest iteration adds “in-network compute," designed to enable both computation and communication functions across accelerators.

Version 2.0 also offers reduced latency compared to the initial iteration, the group claims, along with boosted bandwidth and improved scaling efficiency for distributed training and inference for AI workloads.

“As AI workloads continue to outpace traditional interconnect timelines, we are pleased to deliver an essential update to the UALink Specifications,” UALink Consortium Board Chair Kurtis Bowman noted in a statement. “The advancements to UALink technology introduced in this release will enable the industry to quickly and efficiently integrate UALink solutions into their architectures.”

The UALink Consortium was founded in mid-2024, backed by the likes of AMD, Cisco, and Hewlett Packard Enterprise (HPE) that came together to create an open, low-latency, high-bandwidth interconnect substitute to Nvidia’s NVLink.

Despite the group’s initial standard dropping last spring, little to no 1.0-compliant hardware is available at the time of writing, with most systems still in the production phase. Early efforts have seen UALink IP solutions hit the market from vendors like Synopsys, however, and Keysight moved to get ahead with its UALink 1.0 transmitter testing solution, which debuted late last year.

The Consortium also published a handful of hyper-specific interconnect specifications. Among those include 1.0 versions of its standard for chiplets and centralized control planes, respectively, along with the second iteration of its 200G Data Link and Physical Layers spec.

“The UALink Consortium remains committed to advancing AI infrastructure through open industry standard technology that facilitates next-generation AI applications to the market,” added Bowman, who is also director for architecture and strategy at AMD.

Despite not partaking in UALink for obvious, competitive reasons, Nvidia is playing ball with other industry interconnect efforts like the Ultra Ethernet Consortium, OCP’s Ethernet for Scale-Up Networking (ESUN), and the recently formed Optical Compute Interconnect’s Multi-Source Agreement group (OCI-MSA).

To address the threat of a rival from UALink, Nvidia opted to open its compute fabric to select partners via NVLink Fusion. The likes of Arm, Fujitsu, and Qualcomm count among its early adopters, which will see partner custom CPUs coupled with Nvidia’s GPUs via the chip giant’s interconnect technology.

The most recent NVLink update saw Marvell Technology sign onto Fusion, tapping the platform to connect the latter’s hardware into Nvidia’s AI factory, but also AI radio access network (RAN) architectures.