SK Hynix and Sandisk unveiled the first standard specifications for high-bandwidth flash (HBF), the next-generation alternative to supply chain-constrained high-bandwidth memory (HBM).

The specification was hinted at earlier this year through a consortium to standardize the nascent HBF technology via the Open Compute Project (OCP). The capacity specs cover up to 512 gigabytes across two stack configurations and with bandwidth levels measured across three grades, outlining performance capabilities ranging from 400 Mb/s to 3 Tb/s.

It also makes use of the universal chiplet interconnect express (UCIe) open high-speed interconnection to interlink the memory hardware with accelerators including graphics processing units (GPUs) and central processing units (CPUs).

“With the rapid spread of AI applications, we are at a point where overall data processing structures must be redesigned,” SK Hynix EVP and head of solution development Kim Chun-sung noted. “Through HBF, SK Hynix will expand the boundaries between memory and storage and contribute to building new architectures that enhance overall system efficiency.”

HBF was teased back in February 2025, with Sandisk contending that traditional HBM, which uses dynamic random-access memory (DRAM) at its core, cannot scale physically or economically. Instead, it argued that taking vertical stacking and packaging concepts used for HBM and pairing them with non-volatile (NAND) flash allows for more memory capacity while providing comparable levels of bandwidth – all while maintaining a similar price point.

Sandisk’s Cynthia Hsu in a conversation with SDxCentral earlier this year said HBF was purpose-built for AI inference workloads, while also offering means to significantly reduce energy consumption for memory-intensive workloads.

HBF development efforts were given a lift when Google engineers lauded it for potentially providing 10-times the memory capacity per node for inference workloads. Google was listed as a participant in the HBF consortium per SK Hynix’s announcement, with Jeff Bezos and Samsung-backed AI chip firm Tenstorrent also on board.

Following the launch of the first HBF standard, the memory chip makers said the consortium will work to further expand technical maturity and market acceptance “based on open collaboration.”

“As agentic AI rapidly commercializes, the volume of data to process is surging alongside growing demands for higher speed and efficiency,” the announcement reads. “Recognizing that a single memory type cannot address these complex challenges, both speakers will present the necessity and future direction of a next-generation architecture based on tiered memory, a framework that connects and optimizes diverse memory types into a unified system.”

The first HBF-powered inference devices are expected to sample in early 2027, Hsu outlined back in May, with the OCP collaboration allowing the pair to “move a little bit faster.”

“You don't want to do this in a silo. And we're moving quite fast under OCP," Hsu told SDxCentral. “You won't have to wait too long.”