TAIPEI – Intel put the "X" in Computex with the official launch of its Xeon 6+.

Originally announced in March, the Xeon 6+ (Clearwater Forest) is the first data center CPU to be built on Intel 18A, the most advanced process node from its foundry division.

The new central processing unit (CPU) will be supported by major original equipment manufacturers, including Asus, Dell, Foxconn, Giga Computing, Gigabyte, and Hewlett Packard Enterprise (HPE).

Intel claimed its Xeon 6990E+ delivers 1.3-times higher average performance per thread and 1.3-times performance per thread per watt than AMD's Epyc 9965. Magnus Ewerbring, Asia Pacific (APAC) CTO for Ericsson Taiwan, backed that claim by stating the vendor had seen a 60% increase in performance per watt with the chips.

Discussing the heightened need for power efficiency with AI processing, the exec expects the overall traffic load to triple over the next five years, demanding a “stable and robust architecture” to distribute compute on different parts of the hardware layer.

“That's what we feel we have now in Xeon 6+, where we have hardware support accelerators for certain loads, and then a more general compute for certain loads that gives us flexibility to adapt our application over time as load traffic pattern changes as well," Ewerbring said.

Intel aims for all things agentic

Ewerbring’s remarks came at an Intel-hosted panel held at Computex 2026. There, Kevork Kechichian, EVP and GM of Intel's Data Center Group (DCG), broadcast the company's key message: that the Xeon 6+ line is built for the current agentic era.

“On the telco side, you can have these boxes very condensed with high processing being closer in the field to the antennas," Kechichian said. "It opens up all kinds of new paradigms … we're talking about agent densities and agent densities per rack and agent densities per unit of power. All of this is coming to the forefront because it's relevant to the end user.”

Ewerbring added that with remote radio sites needing power‑efficient and specialized compute for a narrow set of tasks, Intel’s Xeon wares provide a common hardware base for its distributed infrastructure.

“It supports our 5G dual mode core that then will execute in … edge breakout regional central data centers, and it's a hardware base that then fully supports and triggers our application that can either be more centrally produced or locally," Ewerbring said.

The Ericsson CTO also gave the customer view by explaining that choosing compute platforms is highly complex, with at least 15 different parameters to consider and their importance ranked by deployment context, for example, an antenna site or national data center.

“Our hardware engineers need to make sure that whatever comes on the application side some years down the line also has appropriate support from our hardware layer," Ewerbring said. "With the design we have and the hardware support we get from the Xenon 6+, we feel we are on the right trajectory here to support our customers.”

Disaggregation and security

Yujing Qian, VP of engineering for neocloud GMI Cloud, also highlighted security as a top client priority, arguing that confidential-compute CPUs in the Xeon range allow customers to trust their workloads are secure even in third‑party or “anonymous” hyperscale data centers, which is crucial when they’re geographically far from the hardware.

With Xeon’s disaggregated CPU platform designed to work alongside graphic processing units (GPUs) as opposed to replacing them, Qian pointed to the benefits of having the CPU and the GPU “at the same [colocation] in a [cololocation] situation under the same network, so this kind of two-stage CC (confidential computing) can come up as a natural solution.”

Tim Wilson, VP and GM of data silicon engineering at Intel told SDxCentral the Clearwater USP was defined by disaggregation, which would help Intel overcome increasingly ubiquitous supply bottlenecks noted by both GMI Cloud and Giga Computing at the panel.

"When you start to put multiple chips in a package, then the immediate challenge becomes, how do you efficiently move the data between those chiplets? And so you need advanced packaging capabilities to do that [which] Intel has been a leader in," Wilson said. "It's a very power-efficient, dense technology that allows you to move that data back and forth, and so I would say it's extremely valuable in HBM (high-bandwidth memory) heavy designs, and I think it's a capability that Intel Foundry will meet. Our packaging capabilities are a desirable differentiator, not just for our own products, but for external customers coming onto Foundry."