The chips were introduced at the Computex event in Taipei on Tuesday afternoon (Monday after-hours, for those of us in California). They’re the fruits of a project that Cavium announced nearly two years ago, and they represent the company’s first foray into the ARM architecture. Cavium’s Octeon line of multicore chips are based on MIPS processors.
Cavium is joining several other chipmakers, including Broadcom and Freescale, in developing processors based on ARMv8. That’s a relatively new 64-bit architecture meant to swing ARM, best known for teeny processors that go into mobile devices, into heftier jobs, such as running network equipment. (ARM licenses out a microprocessor architecture only, leaving it to other companies to build the actual chips.)
Cavium claims its edge lies in fine-tuning ThunderX variants for specific tasks: compute, networking, storage, and security. Each gets its own version of the chips sporting a different combination of interfaces and features. The networking and security variants (named Thunder_NT and Thunder_SC, respectively) include hardware accelerators, for example.
Cavium is also going big with the number of processor cores it’s putting on a chip — 48, whereas many competing ARM v8 devices are shooting for eight cores. That’s because Cavium isn’t aiming for the same microserver market that other vendors are chasing; rather, Thunder is going after the high end occupied by Intel’s Xeon family, says Rishi Chugh, director of Cavium’s processor group.
All of this could come in handy for housing virtualized network functions for NFV. Early NFV proofs-of-concept (PoCs) were done with x86-based chips, but service providers are interested in trying out ARM as well, Chugh says.
ThunderX — more properly named the CN88xx series — is due to start sampling early in the fourth quarter. A software development kit (SDK) is already out and in the hands of ODMs.
A second generation of ThunderX, then CN99xx series, is slated for 2016 release. Those chips will be based on ARM’s next generation of 64-bit architecture and next-generation I/O, Chugh says.