Intel debuted two infrastructure processing units (IPUs) alongside an updated acceleration development platform during its annual Architecture Day this week.

Intel first teased the IPUs — what the chipmaker has taken to calling its data processing units (DPUs) or smartNICs — at the Six Five Summit in June. IPUs are programmable networking devices tasked with offloading data processing and communication tasks from the CPU, thus freeing up clock cycles for profit-generating workloads.

Intel claims that in modern cloud-native workloads, up to 80% of a CPU may be consumed by input/output (I/O) overheads. By shifting communications workloads off of the CPU and onto the IPU, Intel can free up those resources to run additional application instances and improve the overall efficiency of the data center.

Intel’s latest IPUs, code named Mount Evans and Oak Springs Canyon, launch alongside an updated acceleration development platform called the N6000.

Kicking things off with Oak Springs Canyon, the platform is an evolution of Intel's Agilex FPGA and offers two, 100 Gb/s interfaces worth of infrastructure acceleration. This, Intel claims, makes the card ideally suited to meet the needs of communications service providers as they build out 100 Gb/s networks.

Intel announced Agilex in early 2019, however the chipmaker only recently began shipping the 10-nanometer FPGAs earlier this year with the launch of its Ice Lake Xeon Scalable processors.

Oak Springs Canyon isn’t the only IPU based on an Agilex foundation. Intel’s N6000 Acceleration Development Platform is also derived from the FPGA and includes elements of Intel’s E810 Ethernet controller.

According to Intel, the N6000 is tailored for use in Intel-based servers to help telecom providers accelerate workloads like Juniper’s Contrail platform, Open vSwitch, and segment routing over IPv6 data planes.

Finally, Mount Evans marks a departure from Intel’s previous FPGA-based IPUs and SmartNICs, and instead employs a packet-processing engine built around an ASIC. According to Intel, the platform was developed in collaboration with an unnamed communication service provider in a bid to address long-tail latency challenges associated with lossy networks.

“This ASIC supports many existing use cases, including vSwitch offload, firewalls, and virtual routing, while providing significant headroom for future use cases,” Patricia Kummrow, VP of Intel’s Networking and Edge Group, wrote in a recent blog post.

Additionally, the IPU can emulate NVMe devices at high input/output operations per second (IOPS) using an integrated Optane NVMe controller.

With these IPUs, Intel targets four key applications: accelerated networking, storage, security, and infrastructure processing, Kummrow explained.

While the first three are fairly straightforward, involving the offload of specific functions normally handled by the CPU, Kummrow notes infrastructure processing is “perhaps the most sophisticated usage” for an IPU.

Infrastructure processing involves the offload of hypervisor services and management functions from the CPU to the IPU, she explained.

In fact, this is a key goal in Intel’s collaboration with VMware on Project Monterey, which seeks to offload the software vendor’s vSphere software stack entirely to a DPU or IPU.

Of course, Intel isn’t the only vendor pursuing DPU technology. In fact, the company faces stiff competition from rivals Nvidia, Xilinx, Marvell, and Fungible, which have all announced products promising similar outcomes.

Nvidia, which acquired Mellanox in 2019, recently detailed its third-generation BlueField DPUs. The chipmaker claims the DPU will offload up to 300 CPU cores worth of I/O tasks when it launches in 2022.

Meanwhile, both Marvell and Xilinx recently debuted their own DPUs. Xilinx's latest Versal FPGAs gained high-bandwidth memory, while Marvell announced its Octeon 10 platform for embedded applications like edge switches, SD-WAN appliances, routers, firewalls, and PCIe NIC cards.