Intel today unveiled new field programmable gate arrays (FPGAs) – the Intel Agilex FPGA family – for data- and compute-intensive workloads like artificial intelligence (AI) across the network, cloud, and edge.

An FPGA is an integrated circuit that can be programmed anytime, even after the device has been shipped to customers. Combined with high throughput and very low latency, FPGAs are ideal for many cloud and edge applications.

The new Agilex products combine FPGA fabric built on Intel’s 10-nanometer (nm) process technology with heterogeneous 3D system in a package (SiP) technology for integration. This enables “any-to-any” integration — the capability to integrate analog, memory, custom computing, custom I/O, and Intel eASIC device tiles into a single package with the FPGA fabric. This technology enables customized compute devices, said said Dan McNamara, senior vice president for Intel's Programmable Solutions Group, on a call with reporters.

“This any-to-any integration is really a game changer,” McNamara said. “This is really delivering new levels of flexibility and customization to our customers.”

In addition to the hardware, Intel is launching a software initiative it calls “One API,” which provides a software-friendly heterogeneous programming environment. McNamara said this will make it easier for developers to write code that will benefit from the FPGA capabilities.

CXL Support

The FPGAs also support Compute Express Link (CXL), a cache and memory coherent interconnect to future Intel Xeon Scalable processors.

Last month Intel launched an open source CXL consortium with Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise (HPE), Huawei, and Microsoft.

“Compute Express Link is a technology that exists between the CPU and accelerator — creating a high-speed, low-latency interconnect that removes the bottlenecks in computation-intensive workloads,” Jim Pappas, director of technology initiatives at Intel, told SDxCentral.

Intel developed the technology behind CXL and donated it to the consortium to become the initial release of the new specification. The interconnect between the CPU and workload accelerators such as graphics processing units (GPUs) and FPGAs becomes increasingly important in big-data workloads like AI, machine leaning, media, image and language processing, encryption, and cloud applications.