The Compute Express Link (CXL) Consortium unveiled the fourth iteration of its specification this week, designed to power high-speed, low-latency interconnects for memory and computing hardware.

Unveiled during SC25 in St. Louis, Missouri, CXL 4.0 supports double the bandwidth compared to the prior version, offering up to 128 GT/s with little to no latency. CXL-enabled devices can also move data between one another at fast speeds, which the organization claimed helps to directly improve system performance.

The fourth generation of the CXL specification comes with bundled port capabilities, enabling supported devices to combine ports between host and CXL accelerators to further increase bandwidth connections.

In addition, it’s fully backward compatible with prior iterations of CXL, including 3.x, 2.0, 1.1, and 1.0.

“The release of the CXL 4.0 specification sets a new milestone for advancing coherent memory connectivity, doubling the bandwidth over the previous generation with powerful new features,” said Derek Rohde, CXL Consortium president and treasurer, principal engineer at Nvidia. “This release reflects our member companies’ commitment to driving open standards that empower data center innovation, support compliance and interoperability, and enable the entire industry to scale for future usage models.”

The CXL Consortium was founded back in 2019 to develop open interconnects. Intel led the project, embedding the tech in its data center platforms, including Xeon processors, FPGAs, GPUs, and SmartNICs. The likes of Cisco, Google, and Hewlett Packard Enterprise (HPE) were among the early heavyweights that also got involved.

The group has grown to nearly 200 members, with participants seeking to develop an alternative to the dominant PCI Express (PCIe) technology.

While it’s not directly competing with PCIe, CXL aims to enable a direct memory interface between the CPU and peripheral devices to push beyond bottlenecks found in high performance computing (HPC) applications.