A number of them, including Netronome and Xilinx, presented at a workshop held at Stanford University last week, organized by the nonprofit P4 Consortium. Xilinx showed P4 running a 100-Gb/s data plane on an FPGA, while Netronome demonstrated the use of P4 on a 40-Gb/s network interface card (NIC).
Last week, Netronome also let several dozen developers try the NIC at an invitation-only workshop in San Jose, California (pictured above).
Both chip vendors had also demonstrated at the inaugural P4 gathering in June, but this time they had more company. The workshop had about 200 attendees versus 100 in June, estimates Gordon Brebner, a Xilinx Labs researcher.
P4 originated with research conducted during the last couple of years, and it’s gained attention partly because of the involvement of professors Jennifer Rexford of Princeton University and Nick McKeown of Stanford. Both have been prominent in the SDN community — particularly McKeown, who helped lead the university projects that led to the OpenFlow protocol.
“What caught my attention with P4 is that it’s got Nick McKeown behind it,” Brebner says. “Something similar to OpenFlow is likely to happen with P4.”
Related: P4 Language Aims to Take SDN Beyond OpenFlow
As opposed to OpenFlow, which is a protocol, P4 is a full-blown programming language. Its goal is to provide even more flexibility than OpenFlow does, as OpenFlow is necessarily rigid about things such as the fields required in a packet header.
“The good thing about P4 is that it’s very high-level and very simple,” says Sujal Das, senior vice president of Netronome’s data center business unit. “The issue is that it’s new. It’s still evolving. I don’t think you’ll see production deployments with P4 in 2016 — probably 2017.”
Before we look into Netronome and Xilinx’s products, it’s worth noting that plenty of other groups gave talks and demos at the P4 workshop. Here’s a small sample:
- Huawei explained how it’s linking P4 to its Protocol Oblivious Forwarding (POF) interface
- Corsa demonstrated its Xilinx-based hardware, originally developed for OpenFlow, working with P4
- Intel talked about using P4 with its Data Plane Development Kit (DPDK).
- The University of Massachusetts at Lowell talked about implementing P4 on a graphics chip.
Netronome’s Network Card
At Netronome’s San Jose tutorial, developers worked on a bank of 40-Gb/s NICs, a product that Netronome is sampling and hasn’t announced a production date for.
For Netronome, P4 is part of a broader trend. “More and more, networking such as virtualization, security, load balancing — things that are traditionally done in the switching infrastructure — are moving to the server,” Das says.
The reason this didn’t happen, say, a decade ago, is because packet processing is particularly hard on general-purpose CPUs. This is one reason why Intel’s DPDK exists — to help boost performance of packet processing on an x86.
The alternative that Netronome offers is to plug a NIC into the server, to “free up CPU cycles to run applications and VMs,” Das says.
The workshop led developers through the use of P4 to program the 40-Gb/s NIC. It also included some programming in C, because more complicated tasks — anything that requires keeping track of network state, for instance — is better handled that way, Netronome’s instructors claimed. Having the C environment comes in handy particularly for university researchers who “want to get down-and-dirty with the hardware,” Das says.
Xilinx’s Language Skills
Xilinx, meanwhile, upped its game at the P4 workshop, using P4 to program a 100-Gb/s data path, having shown a 40-Gb/s example in June. (UPDATE: Xilinx tells us it was actually 100 Gb/s that they showed in June.)
It’s the latest stage in a long road for Brebner. He joined Xilinx in 2002, part of a research group trying to prove FPGAs could be useful for packet processing. But finding a data-plane programming language turned out to be a years-long task.
Xilinx tried a couple of alternatives that were being kicked around the industry but eventually decided it had to create its own high-level language. That was PX, which is now a component of Xilinx’s SDNet offering.
“I’d never intended to work on a new language,” Brebner says. “All the time, we were hoping some kind of language would come up for packet processing.”
When the P4 Consortium formed earlier this year, Xilinx wasted no time. It was possibly the first company to join, besides McKeown’s own startup, Barefoot Networks, Brebner says. The draw was not only the language itself but also McKeown’s participation, he says.
“We worked very closely with Stanford over the years, and one of my guys who worked on PX is now working on P4 at Nick’s startup,” Brebner says.
More generally, Xilinx is looking for where it might take SDNet next. “We’re looking for the right time to adapt this with a next-generation declarative language. P4 is one of the candidates,” says Dimitry Vaysburg, who handles product marketing for SDNet.