Intel will develop and manufacture structured ASICs for the U.S. government as part of a three-year partnership with the Defense Advanced Research Projects Agency (DARPA). The project, dubbed the Structured Array Hardware for Automatically Realized Applications (SAHARA), seeks to secure a domestic source of semiconductors for use by the U.S.

DARPA’s decision to partner with Intel should come as no surprise. “Intel is the only domestically owned chipmaker with multiple fabs throughout the U.S.,” said Wayne Lam, senior director of research for the Americas at CCS Insight.

Under SAHARA, Intel will develop structured ASICS, what the chipmaker calls eASICS, for a variety of government applications.

“Structured ASICs have advantages over FPGAs that are widely used in many Department of Defense applications,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office, in a statement. “In partnering with Intel on the SAHARA program, DARPA aims to transform currently fielded, as well as future capabilities, into structured ASIC implementations with significantly higher performance and lower power consumption.”

The program seeks to dramatically shorten the time required to develop ASICs while implementing “unique security features” in support of a zero-trust philosophy, Leef added.

Intel’s structured ASICS fall somewhere between an FPGA and a standard ASICs. The company claims its eASICs are less expensive and easier to develop than traditional ASICS and run at lower power compared to FPGAs. “This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10-nanometer semiconductor process,” said José Alvarez, senior director of Intel’s Programmable Solutions Group, in a statement.

The chips themselves will be built on Intel’s 10-nanometer manufacturing node and feature the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technologies to allow multiple processors to be integrated into a single chip.

These chips will then be hardened against vulnerabilities through collaborations with the University of Florida, Texas A&M, and the University of Maryland. University teams will use various attack strategies to assess the chips for vulnerabilities and develop security countermeasures to be integrated into the final chip’s designs.

Project SAHARA comes amid a semiconductor supply chain shortage that has already hobbled the automotive industry and sparked concerns over the U.S. government’s ability to source silicon from U.S. chipmakers. In late February, President Joe Biden issued an executive order to address the semiconductor shortage and address the associated national security concerns.

“I know the US government is eager to regain some lost ground on the world stage of semiconductor competitiveness. They see it not just as a matter of national pride, but of national security,” said Glenn O’Donnell, VP and research director of infrastructure and operations at Forrester Research.

But while Intel was the obvious partner of choice, O’Donnell warned that the government should be careful in how it supports chipmakers.

“While some support is essential to be competitive with other nations and other companies, direct financial support is a political hot potato,” he said. “Joint development, like this DARPA-Intel deal, and quasi-governmental consortia, like Sematech, are a good approach.”

Intel, Microsoft Team Up to Secure Government Workloads

SAHARA comes a little over a week after Intel signed onto DARPA’s Data Protection in Virtualized Environments (DPRIVE) program, which aims to develop an accelerator for an advanced means of encryption.

The accelerator will eventually be tested and deployed in Microsoft’s Azure to secure government workloads using what’s called fully homomorphic encryption (FHE).

According to Rosario Cammarota, principal engineer at Intel Labs and principal investigator for DPRIVE, fully homomorphic encryption is the “holy grail” when it comes to keeping data secure while in use.

“Despite strong advances in trusted execution environments and other confidential computing technologies to protect data while at rest and in transit, data is unencrypted during computation, opening the possibility of potential attacks at this stage,” he said, in a statement.

However, with fully homomorphic encryption, the system is able to compute workloads without decrypting them at any point in the process. The problem is current implementations introduce massive performance overheads for “even simple operations,” Intel said.

This is where Intel comes in. The chipmaker has been tasked with developing an ASIC to accelerate fully homomorphic encryption (FHE) and mitigate the performance penalty. “When fully realized, the accelerator could deliver a massive improvement in executing FHE workloads over existing CPU-driven systems, potentially reducing the time to processing the cryptograms by five orders of magnitude,” the company claimed.