Forget 7 nanometer or 5-nanometer chips, IBM today unveiled a 2-nanometer chip that packs more than 50 billion transistors into a package the size of a fingernail and promises up to 45% higher performance over the current generation data-center chips.

“The innovation reflected in this new chip is essential to the creation of new, more powerful technology platforms that can help our society address major challenges, from climate and sustainability to food scarcity,” said Dario Gil, SVP and director of IBM Research.

The company sees the new chip as pivotal to reducing data centers' carbon footprint and enabling new technologies like 5G and 6G communications as well as autonomous driving.

If every data center switched from 7-nanometer processors to ones build on its 2-nanometer process, it could save enough energy to power 43 million homes, the company claims.

“This is the world's first test chip with 2-nanometer technology,“ IBM Director of Semiconductors Mukesh Khare said, holding up a piece of silicon the size of his thumb.

Developed at the company’s Albany, New York research facility, the chip is more of a proof of concept than a production-ready process. IBM has a long history of firsts in the semiconductor space. The chipmaker was among the first to develop both 7- and 5-nanometer chips. IBM is set to deliver its first crop of chips based on its 7-nanometer process with the Power10 generation.

IBM’s foundry partner Samsung Electronics will produce the first chips based on the new manufacturing process sometime in 2024, Khare said.

The announcement comes as foundry operators Taiwan Semiconductor Manufacturing Co. (TSMC) and Samsung are racing toward 3-nanometer chips, which are expected to reach production in 2022.

In addition to higher performance compared to the older 7-nanometer process node, IBM is claiming 75% greater efficiency if maintaining the same performance.

Producing chips this small isn’t without challenges, however. Khare notes that at 2 nanometers, the transistors are about the width of two DNA strands, requiring advantaged manufacturing to prevent phenomena like electron leakage.

Electron leakage is just what it sounds like. Transistors are effectively switches that control whether electricity — electrons — is allowed to flow through or not. The problem faced by IBM and other chipmakers is as the transistors get smaller, the easier it is for electrons to slip past the transistor gates. This, Khare said can lead to higher power consumption and reduced efficiency.

“There are a few key features or key enablers that we at IBM Research have been working for several years to ensure that we can meet power and performance requirements for a two nanometer technology,” he said.

One of these enablers is the use of bottom dielectric isolation, which ensures that as the transistors open and close while processing binary functions there is no electron leakage.

Additionally, to produce the chip, IBM employed single-pass extreme ultraviolet (EUV) lithography on the front end of the chip. EUV is used in modern semiconductor manufacturing to effectively etch the nano-scale structures — like transistors — onto a silicon wafer.

Khare explained that EUV has been used in the past, beginning with 7-nanometer generation of chips, for the middle and backend of the chip. “Now we have started to employ, in the 2 nanometer generation, EUV patterning in front end to create structures for the nanosheet or the gate. So, now, all the critical feature for this technology will use UV lithography,” he said.

Finally, IBM’s 2-nanometer chip employs a tweaked voltage control which allows it to scale from low-voltage applications like smartphones and consumer electronics to data center applications.

The proof of concept has implications across the semiconductor industry. The technology will almost certainly find its way into IBM’s Power and Z-series processor families at some point, but the manufacturing technology could see use among the company’s partners as well.

While Khare dodged questions about whether the technology could be made available to Intel, which has struggled to produce chips at 10 nanometers and has heavily delayed its upcoming 7-nanometer tech, the two companies recently announced a joint partnership.

In late March, Intel CEO Pat Gelsinger announced a research collaboration with IBM to develop next-generation logic and packaging technologies at the company’s facilities in Albany, New York and Hillsboro, Oregon.

Whether we'll see Intel chips built using IBM's 2-nanometer technology, however, is yet to be seen.