Intel CEO Pat Gelsinger has, in the span of five weeks, already managed to make his mark on the chipmaker. During a press conference Tuesday, Gelsinger announced Intel would open its foundries to contract customers, invest $20 billion to construct new fabs in Arizona, and contract with outside foundries, including Taiwan Semiconductor Manufacturing Co. (TSMC), for a growing number of products.

The news, which has been met with cautious optimism from analysts, comes as Intel faces its stiffest competition in years amid repeated product delays, an executive shakeup, and the ousting of former CEO Bob Swan.

Patrick Moorhead, president and principal analyst at Moor Insights & Strategy, appreciates Gelsinger’s honest appraisal of Intel’s situation

“He exudes senior-level technical and execution confidence and openness that I haven’t seen at Intel for years,” Moorhead wrote in an article contributed to Forbes. “Gelsinger said all the right words and gave me all the reasons to believe that Intel is ‘back,’ but now needs to execute.”

Pund-IT analyst Roger Kay expressed similar enthusiasm following the press conference. “Gelsinger gave one of the most momentous speeches I’ve heard in my decades in the technology industry,” he wrote.

Key to Intel’s foundry push and its Integrated Design Manufacturer 2.0 (IDM 2.0) initiative, is a $20 billion investment in two new semiconductor foundries in Intel’s Ocotillo campus in Arizona. Gelsinger said the company will also be looking to add additional foundries in the U.S. and Europe, regardless of state or federal incentives.

“The $20 billion doubling down of manufacturing is bold and is intended to serve its internal uses and be used for its own Intel Foundry Services,” Moorhead wrote. “This isn’t Intel hedging its manufacturing bets, it looks to me as if the company is all in.”

“I was pleased to hear that the $20 billion investment is not determinant of any government funding, but I believe Intel should get funding by both the U.S. and the E.U. to build more capacity more quickly,” Moorhead added.

However as several analysts pointed out, this isn’t Intel’s first go at entering the foundry business.

“Critics would argue that elements of this strategy aren’t new,” CCS Insight CEO Geoff Blaber explained an email to SDxCentral. “Intel has talked about opening its manufacturing capability to customers for years but failed to make any considerable progress.”

IDM 2.0 and Intel’s $20 billion investment in new fabs is a good start, but the company still has a long way to close the gap with TSMC and bring customers to its foundry business, according to Blaber.

Intel’s most advanced manufacturing process caps out at 10 nanometers. Meanwhile, TSMC and Samsung Electronics are shipping 5-nanometer products, with 4-and 3-nanometer chips slated for 2022.

”Gelsinger needs to prove that this time is different, that it fulfills a customer need, and that it can sit comfortably alongside Intel’s own manufacturing requirements,” Blaber wrote.

Moorhead, however, offers a slightly more optimistic take on Intel Foundry Services.

“This is the first time Intel is seriously doing what it needs to create what I consider a ‘real’ foundry,” he wrote, pointing to Intel’s adoption of standard process design kit models, design rules, and tools from Cadence and Synopsys.

“That is a requirement for other foundry customers who already use those models, rules, and tools, and enables import to and express designs from TSMC, Samsung, [United Microelectronics Corp] and GlobalFoundries,” Moorhead added.

Most of Intel's 2023 product roadmap will still be built in Intel fabs, but some client and data center products will be outsourced to companies like TSMC where necessary, Gelsinger said.

The Intel chief notably blamed the chipmaker's challenges with its 7-nanometer manufacturing process on missteps it made in implementing extreme ultraviolet (EUV) lithography.

“When Intel initially designed 7 nanometers, EUV was still a nascent technology, so we developed our process to limit the use of EUV,” he said. The side effect of this was increased process complexity, which had a domino effect, delaying the company’s current generation 10-nanometer chips, he explained.

Intel was, after a six-month delay, able to rearchitect its 7-nanometer process to make better use of EUV lithography and promised a return to a yearly tick-tock cadence, Gelsinger said.

“I have become more confident with Intel’s 7-nanometer plans given it's sticking with it's revised schedules and it's increased use of EUV, which should simplify the manufacturing process and should improve efficiency when it is released,” Moorhead noted.

While it's not yet clear how Intel will decide which chips to manufacture internally and which to outsource to TSMC, Moorhead expects the chipmaker to contract out its highest performance CPUs. “It will be interesting to see both AMD and Intel CPUs on TSMC’s 3-nanometer process head to head," he wrote.