IBM is continuing to advance its research and development efforts into the nascent domain of chiplets.

This week, IBM published new research into an innovative bonding technique that could reduce the size needed to connect multiple chiplets, potentially enabling greater density and computing power. The promise of chiplets is a smaller silicon chip design than the common system-on-a-chip approach used today.

“The idea behind chiplets is to break apart a system on a chip (SoC) so that a chip comprised of chiplets could be made using mix-and-match components sourced from multiple providers," Dale McHerron, Ph.D., senior manager of Process Strategy at IBM, told SDxCentral. "The benefits to this system could be huge — from entirely new computing paradigms, to more energy-efficient systems, to shortening system development cycle time, to more affordable chips."

IBM produces a few different types of silicon today, including the Power architecture that is used in production.

McHerron noted that currently, IBM’s work in the chiplet space is actively in the research and development phase and hasn't reached production yet.

"Before we can adopt a chiplet ecosystem, the industry will need a standardized framework for designing chiplets," McHerron said. "There are currently two leading initiatives — Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW) — and IBM is involved in both."

McHerron said that IBM researchers have started exploring various designs for chiplets based on where the two groups are headed. IBM is also working on signal-mapping strategies in the context of potential future chiplet packaging solutions, and looking into which next-generation technologies can advance the concept of 3D chiplet stacking.

"It’s also helpful that IBM’s chip packaging facility in Bromont, Quebec, is the largest in North America," he said.

The new innovation detailed this week by IBM is for a technique known as hybrid bonding.

McHerron explained that hybrid bonding is a new way that chiplets could be bonded together in a 3D chip stack. Instead of solder-based interconnections, hybrid bonding fuses copper and inorganic dielectrics in layers. The result is a bond between chiplets that’s only around 1 micron, compared to tens of microns for solder-based interconnections. This enables a significant reduction in the size and pitch of these interconnections, which will enable much higher communication bandwidth between the stacked chiplets.

The hope is that the new hybrid bonding method has the potential to increase the data throughput between chiplets, and the number of chiplets that could be stacked in a given space, creating a chip from chiplets that can act more like a single system on a chip.

"We believe that this method would allow chiplets to be built and bonded together at scale," McHerron said. "Hybrid bonding could create systems that act as if they were part of a single chip, instead of distinct chiplets."