Synopsys has expanded its hardware-assisted verification portfolio with the introduction of the HAPS-200 prototyping and ZeBu-200 emulation systems. These new systems utilize the AMD Versal Premium VP1902 adaptive SoC and aim to enhance performance and scalability for complex system-on-chip (SoC) designs.

The HAPS-200 prototype system is said to provide improved runtime performance, faster compile times, and enhanced debug capabilities, featuring up to 4X improved debug performance compared to its predecessor, HAPS-100. It supports scalable configurations from single FPGA to multi-rack setups, with a capacity of up to 10.8 billion gates.

Similarly, the ZeBu-200 emulation system offers a capacity extension up to 15.4 billion gates, while achieving up to 2X higher runtime performance compared to the previous ZeBu generation. This system includes improved debug bandwidth and memory capabilities, with up to 200 GB debug trace memory per module.

Ravi Subramanian, chief product management officer at Synopsys, stated, “With the industry approaching hundreds of billions of gates per chip, verification of advanced designs poses new challenges. Our partnership with AMD continues to ensure that we deliver high performance in hardware-assisted verification solutions.”

Support for these advancements comes from industry partners, including AMD, NVIDIA, and Arm. NVIDIA's vice president of hardware engineering, Narendra Konda, noted that the HAPS-200's speed is crucial for enhancing the productivity of software development teams scaling with AI requirements.

The new systems are built on Synopsys' EP-Ready Hardware platform, which allows for the flexibility of emulation and prototyping without the upfront requirement to balance hardware needs. The HAPS-200 and ZeBu-200 systems are available now for early access customers.

Overall, these developments aim to assist engineering teams in tackling verification challenges in multi-die architectures and accelerating the time to market for new designs.