SAN JOSE, California — The Open Compute Project (OCP) Global Summit rolls into Silicon Valley this week, which means chipmakers are showcasing their new open hardware. And this includes Marvell, which announced its 400 Gb/s silicon for switches targeting edge data centers and 5G applications.

Additionally, Netronome unveiled new network interface cards (NICs) for hyperscalers that offload processing tasks that the CPU would normally handle. These SmartNICs perform Transport Layer Security (TLS)-based cryptography, and the vendor says they are the industry’s first crypto-enabled SmartNIC for OCP servers.

Also, Stordis launched two bare-metal switches powered by programmable Barefoot Tofino ASICs. These are geared toward telecommunications providers deploying 5G networks.

The new Marvell Prestera CX 8500 switch family supports 32 ports of 400 Gb/s or 256 ports of 50 Gb/s network throughput and bandwidths up to 12.8 Tb/s.

The chipmaker also overlaid two homegrown technologies on top of its silicon. Its Storage Aware Flow Engine (SAFE) technology enables virtual storage orchestration by providing greater insight into network flows with per flow visibility, advanced telemetry, and comprehensive diagnostics that identify and resolve network congestion.

The second is called Forwarding Architecture using Slices of Terabit Ethernet Routers (FASTER). This technology adds high radix cores and congestion-aware load balancing. It also enables virtualization for scalability, which results in a reduction in the number of network layers. This lowers latency and reduces complexity, said George Hervey, principal architect at Marvell.

“Every layer of networking really is the cause for latency because it is a potential congestion point,” he said. And by collapsing edge data center networks into a single layer, companies can reduce space and power usage. All of these benefits combine to reduce overall network costs by more than 50 percent, the company claims.

Also at OCP Global Summit today, Netronome unveiled its Agilio CX 50GbE SmartNICs. In addition to the SmartNICs’ cryptography the 2 GB onboard double data rate (DDR) memory can reduce application tail latency by up to 400 percent, the company claims.

Tail latency refers to how the slowest device to respond delays the entire application. This is important because every “web 2.0” application like Twitter or Facebook “has many ‘sub’ applications and transactions that must occur before the overall application can be presented to the user,” explained Ron Renwick, vice president of products at Netronome. “Those sub-applications can be things like images, video, advertisements, etc. The last network packet to arrive gates the entire application delivery — that is tail latency.”

Renwick says systems like an OCP Yosemite server that has one network card feeding four servers can exacerbate the problem. But server designs like Yosemite provide significant price and performance benefits to hyperscalers. Netronome solves this tail latency problem in these types of OCP servers where a 50 Gb/s input feeds four servers with PCI Express connections from the network card.

Additionally, Dynamic eBPF-based programming and hardware acceleration enables intelligent scaling of networking workloads across multiple host CPU cores, which improves server efficiency. The SmartNICs also boost security and data center efficiencies by offloading TLS, a widely deployed protocol used for encryption and authentication of applications that require data to be securely exchanged over a network. This makes it easier for hyperscalers to prevent network hacks — and attacks such as BGP hijacking, when attackers maliciously reroute internet traffic — and better secure user data.

“Netronome has developed the Agilio CX 50GbE SmartNIC solution to address these vital industry requirements by meticulously optimizing the hardware with open source and hyperscale operator applications and infrastructures,” said Sujal Das, chief marketing and strategy officer at Netronome, in a statement.

Stordis also unveiled two bare-metal switches at OCP that are powered by Barefoot’s programmable Tofino networking ASIC and use Barefoot’s open source P4 programming language.

The company says its Stordis Advanced Programmable Switches (APS) offer support for 1588v2 time synchronization, also called Precision Time Protocol. This protocol is designed to enable users to program more advanced (often application-level) functionality into the network. For example, accurate time stamping enables more efficient 5G features development in telco environments, IP studio, and live digital broadcast for media companies, and can be essential for accuracy within financial trading environments.

The switches also provide more powerful processing, higher memory, and greater in-built storage capacity. Both support speed up to 100 Gb/s.