Keysight Technologies has launched Chiplet PHY Designer 2025, a new solution aimed at enhancing high-speed digital chiplet design for artificial intelligence (AI) and data center applications. The updated software now supports the latest Universal Chiplet Interconnect Express (UCIe) 2.0 standard and the Open Compute Project Bunch of Wires (BoW) standards. This advanced tool enables pre-silicon validation, which streamlines the design process and reduces risks associated with semiconductor development.

As the complexity of AI and data center chips increases, ensuring effective communication between chiplets is essential for maintaining performance. The industry's adoption of emerging standards like UCIe and BoW will facilitate interoperability among chiplets in advanced 2.5D and 3D packaging. By ensuring compliance with these standards, designers can significantly mitigate costs and risks involved in the development process.

Chiplet PHY Designer 2025 offers a suite of features designed to improve the design workflow:

• Ensures interoperability by verifying designs against UCIe 2.0 and BoW standards.
• Accelerates time-to-market through automated simulation and compliance testing setups.
• Enhances design accuracy with detailed analysis of signal integrity and bit error rate, minimizing the need for costly silicon re-spins.
• Optimizes clocking designs to ensure synchronization in high-speed interconnects.

Hee-Soo Lee, High-Speed Digital Segment Lead at Keysight electronics design automation (EDA), emphasized the significance of this release: “Chiplet PHY Designer enables chiplet designers to rapidly and accurately verify their designs against evolving specifications. With this update, engineers can continue to save time and avoid rework, ensuring their designs succeed before manufacturing.”

Keysight will showcase Chiplet PHY Designer at DesignCon, scheduled for January 29-30, 2025, at the Santa Clara Convention Center.