Intel asserted its claim over the open and virtual radio access network (RAN) markets at MWC Barcelona 2022 where the chipmaker unpacked a bevy of telco-focused silicon.
The updates included a pair of new Xeon D processors, specifically optimized for SDN and edge applications, including RAN, network edge, and artificial intelligence (AI).
Intel claims the new chips address growing demand for edge compute, with the chipmaker expecting more than half of all data processing to take place outside of traditional data centers by 2025.
“One of the hottest workloads is inference,” Dan Rodriguez, corporate VP of Intel’s Network Platforms Group, said during his keynote. “Think about all the examples, factories examining products, retail stores that are monitoring inventory and foot traffic, communities creating smart and safe places for residents, networking applications and crypto, and packet processing like SASE and SD-WAN.”
Telco Optimized XeonsThe new Xeon D processors are designed to realize this opportunity, and introduce a number of new features intended to make them attractive to network operators, including specialized AI accelerator blocks with support for 512-bit advanced vector extensions (AVX 512).
AVX 512, which is designed to accelerate large vector calculations common in machine learning workloads, has been Intel’s trump card over rival AMD for some time. However, AMD will launch its first chips with AVX 512 support later this year.
Intel’s Xeon D-1700 and D-2700 processor families bring these AI capabilities to the networking and edge markets.
It’s the “first Intel SoC designed from the ground up for software defined network edge,” Rodriguez said.
In addition to AI, the processors also sport an integrated Ethernet controller capable of supporting connections up to 100 Gb/s. This eliminates the need for standalone NICs in space- or power-constrained applications, where high throughput may still be required.
However, for applications that do require external expansion cards, the chips support up to 56 PCIe Gen. 4.0 lanes and SKUs ranging from four to 20 processor cores.
These chips are also Intel’s first Xeon D processors to feature the company’s 10-nanometer Sunny Cove core architecture, which offers significant power savings and performance advantages over older 14-nanometer designs.
This is the same core architecture powering Intel’s third-generation Xeon Scalable processors announced last year. Sunny Cove actually made its appearance more than two years ago in Intel’s 10th generation Core-series mobile processors.
Intel Teases Sapphire Rapids vRAN PotentialIntel’s telco-focused Xeons won’t be stuck with a nearly two year old architecture for long. At MWC Barcelona, the chipmaker offered a glimpse into the expanded role its next-generation Xeon Scalable processor family will play in the virtual RAN and open RAN space.
“In the march towards software-defined everything, vRAN is inevitable, but 10 years ago it was unthinkable,” said Nick McKeown, SVP of Intel’s network and edge group.
The architecture will be among Intel’s most radical to date and see the chipmaker abandon its long heritage of monolithic dies in favor of an AMD-style chiplet architecture.
The new chips, slated for release early this year, are expected to offer significantly higher core counts, support for on-die high-bandwidth memory (HBM), DDR5 memory, and PCIe Gen. 5.0.
And at MWC Barcelona, Intel revealed for the first time plans for telco-specific SKUs with silicon-level optimizations for RAN signal processing and support for large massive MIMO deployments, including 64 transmit, 64 receive antenna arrays.
Intel claims these signal processing optimizations will allow for a twofold improvement in network capacity over previous generation Xeon Scalable processors.
The chipmaker said it’s currently working with Samsung, Ericsson, and Rakuten Symphony, among others to trial the processors in vRAN applications.
Intel’s OpenVINO Gets a BoostOn the software front, Intel announced its biggest update to its OpenVINO software development kit in nearly three years.
The toolkit includes accelerators and is intended to stream deep-learning workloads across Intel architectures.
The updates include simplified APIs designed to make it easier for users to import TensorFlow models and improve code portability. It also features enhancements for natural language processing, double precision, computer vision, and other models well suited to edge deployments.
New modules have also been introduced to ensure customers can take advantage of the AI capabilities baked into the latest Xeon processors. These allow users to accelerate 5G user plane function workloads at the edge, something Intel claims will reduce latency and bandwidth consumption.
As part of the OpenVINO revamp, Intel touted American Tower and Zeblok, which are using the platform to launch what they’re calling an “AI microcloud.”
Arm Targets Open RAN MarketWhile Intel remains a major player in the emerging open RAN market, it’s facing growing competition from Arm chipmakers.
Arm Holdings formally joined the O-RAN alliance in 2020, and last year, the company opened an Arm 5G Solutions Lab in collaboration with Tech Mahindra with the express goal of eliminating barriers to developing Arm-based RAN products.
While Arm is best known for the processors that power the majority of consumer electronics today, the company claims its chips are also at the heart of most traditional RAN infrastructure from companies like Ericsson or Nokia.
“Arm is a leader by a mile here,” Panch Chandrasekaran, director of 5G carrier infrastructure at Arm, told SDxCentral late last year. “Generally, if you open any base station, odds are you’ll find an Arm-based CPU architecture inside.”
Where Arm has less of a stranglehold is in disaggregated and virtualized RAN implementations, like open, virtual, and cloud RAN.
“We believe Arm is in a unique position in the industry to drive this innovation in open and vRAN by removing a lot of the friction that exists today for a multi-party collaborative environment,” Chandrasekaran said.
Amazon has already made inroads in the open RAN space through its Graviton2-based AWS Outposts offering. Meanwhile, Arm is gearing up for a wave of purpose-built open RAN chips based on its freshly revamped Neoverse architecture.