When the Compute Express Link (CXL) Consortium was formed in March, it made waves not only for its lofty aspirations but for the sheer amount of support it received. The proposed interconnect technology seeks to enable a direct memory interface between the CPU and peripheral devices.

And right out of the gate, CXL garnered support from some of the heaviest hitters in the industry. Founding members included Intel, Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise (HPE), Huawei, and Microsoft. During the months since then, the consortium's membership has ballooned to include AMD, Arm, IBM, Nvidia, Lenovo, and 55 other organizations.

The second version of the CXL standard is under development should be available to members during the second quarter of 2020, said Jim Pappas, director of technology initiatives at Intel and chairman of the CXL Consortium. The first CXL hardware will likely hit the market in 2021, he said.

The open standard seeks to address limitations with the now dominant interconnect technology, PCI Express (PCIe), which in recent years has become a bottleneck, especially in high-performance computing (HPC) applications.

CXL isn't, however, competing with PCIe. The two technologies will actually co-exist on motherboards sharing the same 16x card slots popularized by PCIe.

CXL picks up PCIe slack

While PCIe – now in version four – still offers a good amount of bandwidth, it can’t communicate at the memory level. Instead, information has to be shuffled through the input/output (I/O) bus on the motherboard, slowing things down considerably.

In an interview with SDxCentral, Pappas likened PCIe to packing a box full of water bottles and carrying it across the room to its recipient. Whereas with CXL, the bottle is effectively teleported to its recipient, he explained.

“When you compare an SSD (solid-state drive) to the speed of the CPU and memory system, it's about 100 to 1,000 times slower. A hard drive is about a million times slower,” said Pappas. “The I/O buses were built for I/O devices.”

SSDs have maneuvered around this because bandwidth has steadily improved, and latency can be masked by parallelization, he explained. “But when it comes to memory, there is no place to hide latency."

Benefits for HPC & hyperscalers

This has big beneficial implications for a wide range of industries, including HPC and hyperscalers like Google, Amazon, and Microsoft.

One of the limiting factors of servers today is the finite amount of memory a CPU can address on a motherboard – there are only so many dual in-line memory module slots to fill. However, on a CXL-compatible server, more memory can be plugged into an open PCIe slot – the same way a graphics processing unit (GPU) or field-programmable gate array (FPGA) is today.

This framework, according to Pappas, stands to significantly amplify the amount of addressable memory, and it enables large pools of persistent memory. CXL has aspirations beyond memory, too.

The group is eyeing opportunities for other peripherals, including GPUs, FPGAs, and Ethernet NICs, according to Pappas and Barry McAulliffe, president of the CXL Consortium board. In theory, CXL could enable a direct memory interface over high-speed Ethernet, allowing for even more distributed systems, they added.

All major chip makers, including Intel, which developed the technology, AMD, Arm, and IBM, are expected to support CXL. Several other companies, including composable infrastructure vendor Liqid, have also announced support for the standard in part, because it allows for the complete dissociation of memory from the CPU.