Cisco added three new members to its Silicon One family this week, bringing the total to 10 chips launched since it introduced the initiative in 2019.

At the top of the stack is the G100, which is a web-scale switching chip capable of 25.6 Tb/s of throughput, making it the highest bandwidth capacity of any chip in the Silicon One family.

"Cisco now provides the leading routing and web-scale switching silicon," wrote Rakesh Chopra, Cisco fellow of common hardware group architecture and platforming, in a blog post. "With this new device, customers no longer need to choose between programmability, bandwidth, and efficiency."

Cisco claims the chip will eventually allow for 1.6 Tb/s interfaces — four times that of 400 Gb/s Ethernet commonly used today. However, in the near term, Cisco claims customers will be able to deploy routers and switches with up to 256, 100 Gb/s interfaces or 32, 800 Gb/s interfaces, thanks to the use of 112 Gb/s level-four pulse-amplitude modulation (PAM4) serializer/deserializers (SerDes).

In addition to the G100, Cisco launched the Q211 and its L-series switching counterpart, the Q211L. Both Q211 variants are capable of 8 Tb/s of throughput and slot in between the 12.8 Tb/s Q200 and 6.4 Tb/s Q201 chips that Cisco announced back in October.

Like its siblings, The Q211L offers support for large-scale tables, network and port address translation, as well as Cisco’s advanced SmartTOR capabilities. The latter of which allows customers to “optimize their network performance by using our advanced hierarchical traffic manager, fully shared packet buffering, and hierarchical equal-cost multi-path engines,” wrote Chopra.

Meanwhile, the Q211, enjoys many of the same capabilities of its L-series brother, but adds an even larger table scale and deep packet buffers for routing applications, Chopra explained, adding that the chip is optimized for fixed systems with a combination of 10 Gb/s and 400 Gb/s Ethernet ports.