Alphawave Semi has introduced the industry’s first 64 Gbps Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP subsystem, following the successful tapeout of its Gen2 36 Gbps UCIe IP on TSMC’s 3nm technology. This advancement sets a new benchmark for ultra-high-performance D2D connectivity, building on Alphawave Semi's previous generations.

The new Gen3 64 Gbps IP subsystem boasts bandwidth density exceeding 20 Tbps/mm, while maintaining low power requirements and latency. It is designed to support a variety of protocols, such as AXI-4, AXI-S, CXS, CHI, and CHI-C2C, catering to the increasing demands of high-performance connectivity in fields like High-performance computing (HPC), data centers, and Artificial Intelligence (AI).

The design aligns with the latest UCIe specification, featuring a scalable architecture equipped for advanced testability through live per-lane health monitoring. This robust foundation fosters an open and interoperable chiplet ecosystem.

UCIe D2D interconnects facilitate various connectivity scenarios, such as linking compute chiplets for low-latency connections and integrating with I/O chiplets via UCIe interfaces with PCI Express (PCIe), CXL, or Ethernet. The architecture supports optical retimers that can enhance reliable, low-latency optical I/O links, promoting the development of high-speed, low-power solutions in data centers and AI systems.

With high-performance applications in mind, a custom High Bandwidth Memory (HBM) base die using the UCIe standard permits tight integration of memory and compute dies, significantly optimizing memory transactions crucial for AI applications.

Brian Rea, chair of the UCIe Consortium Marketing Work Group, emphasized the milestone achievements such as tapeouts, which highlight increasing adoption of the UCIe specification, a critical development for the chiplet industry. Mohit Gupta, Senior VP and GM at Alphawave Semi, noted that the successful tapeout of the Gen2 UCIe IP sets the stage for the Gen3 64 Gbps offering, aimed at fulfilling high-performance bandwidth needs for customers in 2025.

This initiative positions Alphawave Semi as a leader in high-performance chiplet connectivity solutions, reinforcing its rapid advancements in providing comprehensive silicon-proven connectivity IP subsystems tailored for hyperscaler and data-infrastructure markets.