The editors at SDxCentral have been writing some stories about semiconductor companies and how these companies’ products relate to our coverage of next-generation networks. You can find all these stories, covering Intel, Broadcom, Qualcomm, Arm, and Marvell, here. And we have more in the pipeline.

In the process of writing these stories, we’ve come across some news. For instance, Marvell said it was nixing its Xpliant programmable chip that it inherited in its acquisition of Cavium.

And this week, due in part to extreme nerdiness on my part, I learned about a group that’s working on an open source instruction set architecture for silicon. On Wednesday after I published my story about Arm, someone emailed me saying he liked the story and inviting me to come to a special chips event at Stanford University. I told him I lived in Denver, so I couldn't attend. But then he said it was also being live-streamed.

And at 8 p.m. MST, some mysterious impulse overtook me, and I actually tuned in to a livestream panel where five guys talked about silicon chips. On my free time.

My co-workers suggested perhaps I need an intervention.

The panel was entitled “Bringing Silicon Back to Silicon Valley,” and the participants discussed RISC-V, an initiative to create a free and open instruction set architecture. Some chips, such as Intel’s x86, use complex instruction set computing (CISC) architecture. And some chips, such as many Arm-based chips, use reduced instruction set computing (RISC). The RISC-V group adopts the RISC nomenclature, adding the Roman numeral V.

RISC-V (pronounced “risk-five”) hopes to enable a new era of processor innovation through open collaboration. The group was founded in 2015 and now counts more than 100 member organizations whose employees bring both hardware and software expertise.

“The CPU is the thing that executes the processor; it has a particular instruction set,” said Linley Gwennap, principal analyst with The Linley Group, who moderated the Stanford panel. “The most popular instruction sets are Arm, and Intel has the x86 architecture. The x86 is basically a closed architecture in that only Intel and AMD can produce it. Arm licenses its instruction set and CPUs to other companies to build their own chips. RISC-V is a complete instruction set for building common CPUs. This is not the first time we’ve had an open source instruction set. But it’s the first that’s gotten a lot of traction.”

Krste Asanovic, a professor at UC Berkeley, said, “RISC-V came out of my research group at Berkeley. Asanovic, who is currently the chairman of the board for the RISC-V Foundation, has also started his own company SiFive, which is building an open source chip platform.

“It’s a great time right now,” said Asanovic. “There is a perfect storm in the semiconductor industry. The markets are getting fragmented There’s a demand for custom silicon. Standard parts are not scaling.”

He said companies like Apple and Tesla are building their own chips for their own products. But they don’t sell their chips. He said there are a lot of skills necessary to build a chip, and it’s very expensive. SiFive aims to bring these skills together.

Art Swift, the VP of marketing for Esperanto, said the company has chosen RISC-V to develop its high-performance, energy-efficient computing solutions. “We embraced RISC-V, and for us it has been a fantastic choice. The idea of being able to innovate on an open source platform, wow. It’s a beautiful model, and it encourages innovation.”

Western Digital is seeding RISC-V with initial capital. Kaushik Roy, senior director of corporate development and strategy at Western Digital, said, “There wasn’t a lot of innovation in processor technology. There are only a handful of processor-related startups. That’s the reason we decided to seed the RISC-V ecosystem.”

To tamper all the enthusiasm a bit, the panel also included John Heinlein, chief of staff to the CEO at Arm. Heinlein said Arm already knows that it’s important for customers to customize their chips. “Arms’ model is built around that,” he said. “We just disagree at what level you want to customize. We have an architectural review board to say ‘Where are the trends going?’ and to be sure we put them in our architecture.”

Of the RISC-V initiative, Heinlein said, “Free is not free. When you get a free processor you have to do a lot of work. I would be using this all day long for research. But when you get into commercialization, there are some issues.”

And the analyst Linley added, “There are some drawback to using RISC-V. The open source cores that are available today are pretty low performance. Some of these open source CPUs don’t have all the same features as a commercial design.” He said it’s very expensive to design an SoC. “Whether you want to risk your design on an open source CPU is a tough decision,” Linley added.