RISC-V (pronounced risk five) is getting a big boost this week with its launch of the RISC-V Software Ecosystem (RISE).

RISC-V is an open-source instruction set architecture (ISA) that emerged in 2018 and has steadily advanced over the last several years. RISC-V is a silicon architecture competitive to x86 and, as a reduced instruction set computer (RISC) architecture, is somewhat similar to ARM, IBM's Power, and Oracle’s SPARC. In contrast to earlier versions of the RISC architecture, RISC-V is a completely open-source and readily accessible design.

Multiple vendors have backed RISC-V to date; in 2022, SiFive, which is developing RISC-V hardware, raised $175 million in funding. That same year, Intel announced that it would support RISC-V hardware development as well.

Overall development of the specifications are driven by the RISC-V International organization, but there’s a need to help advance open-source software development in general. That's where the new RISC-V Software Ecosystem (RISE) effort, run by Linux Foundation Europe (LFEU) comes into play. RISE benefits from the participation of Andes, Google, Intel, Imagination Technologies, MediaTek, Nvidia, Qualcomm Technologies, Red Hat, Rivos, Samsung, SiFive, T-Head and Ventana.

"The RISC-V software ecosystem (RISE) is a fancy way of saying basically, industry leaders are coming together to make sure we have commercial-grade software for RISC-V," Amber Huffman, chair of the RISE Project, told SDxCentral. "When you're trying to deliver commercial-grade, hardened performance, low-power secure software, you really need to take it to that next level, so what you have here is industry leaders coming together to try to do that hardening.”

To date, there hasn't been a fully coordinated effort in building foundational open-source tools for RISC-V.

Huffman noted that for important things like system libraries, compilers, debuggers, profilers and emulators, many companies to date had been duplicating efforts as there wasn't a unified approach in open source.

"We weren't really getting things done most efficiently," Huffman said.

With RISE, the group is identifying the key categories where open-source software needs to be enhanced with RISC-V support. The group isn't looking to create entirely new tooling, but rather will be aiming to participate in existing open-source projects such as the GCC compiler, Linux operating system, Python programming language and others, by way of developing and contributing support.

Peter Lewin, director of CPU ecosystems at Imagination Technologies, told SDxCentral that the members of RISE all have a common interest in making sure there is good quality software support for RISC-V.

"In the past, we'd be making an investment ourselves in software for RISC-V, but that has duplicated the work of other people in some places," Lewin said. "So this is about coordination — making sure we can get together as an industry, deciding what the most important bits are that we really need for good quality support, and making sure that we're pulling in the same direction and getting that support as quickly as possible."

RISC-V is already widely used in the embedded space and has found its way into networking gear as well.

Huffman commented that RISC-V is used today for networking ASIC and FPGA applications. Networking interface cards (NICs) can have RISC-V cores as well. RISE can potentially bring better support for those networking use cases as the project builds out its operations. There is also potential for mobile and client applications support for RISC-V that could be running anywhere from the edge to the data center.

RISC-V will compete in some respects against x86 as well as ARM in different deployments.

"What we see is an opportunity for people to choose the right processor for the right application," Huffman said. "We're just getting into this mix-and-match world where you're going to pick the right thing for the right application and who knows what amazing companies will bring to us on what architectures."