Marvell celebrated the close of its $1.1 billion acquisition of Innovium today with the launch of its first 5-nanometer switch silicon and data processing units (DPUS). The chipmaker claims the new products offer 50% lower power consumption than its competitors.

The Prestera DX 7321 Ethernet switch chip features 56-Gb/s pulse-amplitude modulation (PAM4) serializer/deserializers (SerDes), which allow the chip to offer port speeds ranging from 1 Gb/s to 400 Gb/s with aggregate bandwidths ranging anywhere from 200 Gb/s to 1.6 Tb/s.

Announced in late 2020, the chip goes toe-to-toe with Broadcom’s Trident family of switches and targets carrier switching applications, including 5G fronthaul, radio access network (RAN), open RAN, virtual RAN, multi-access edge compute, data center interconnect, and edge connectivity.

To support these use cases, the chip features integrated class-D precision time protocol, MACSec encryption, and telemetry tracking. This, the company claims, allows the switch to support larger cell coverage areas while also improving network visibility and automation.

The Prestera DX 7321 addresses carrier requirements for a high-performance, low-power switch for 5G and data center infrastructure, Marvell claims.

Power consumption was a major focus for Marvell with this generation of Prestera switches, said Nigel Alvares, VP of solutions marketing at Marvell.

“The biggest value of the switch, outside of having the right port count and capacity count, is really the power savings,” he said. “That ties to 5 nanometer with our DPUs. About a year ago we made a big investment partnership with TSMC to move our portfolio to 5 nanometers because of power.”

He added that as open RAN gains momentum, carriers are going to require smaller, more efficient appliances powered by chips like the Prestera DX 7321.

The new chip launches alongside Marvell’s Octeon 10 DPUs, announced this summer. The DPU is designed to intelligently offload data processing and communication tasks from the CPU, thus freeing up clock cycles traditionally consumed by input/output (I/O) overheads.

The chip is available in both a PCIe NIC form factor and a standalone package for embedded appliances like edge switches, SD-WAN appliances, routers, and firewalls.

The DPU can be specced with up to 36 ArmV9 Neoverse N2 processor cores, with support for DDR5 memory and PCIe 5.0 connectivity. The chips also feature an on-die 1Tb/s switch and hardware acceleration for IPsec, machine learning, and vector package processing.

“The combination of these N2 cores and 5 nanometer really is giving us a very strong performance per watt, and that’s something very critical for the applications we’re targeting,” John Sakamoto, VP of Marvell’s infrastructure processor business unit, told SDxCentral in an earlier interview.

On the low-end, Octeon 10 sips just 10 watts of power, while the chipmaker’s top-tier 36-core cards can chew through 60 watts of power.

The product launches coincide with the close of Marvell’s acquisition of switch ASIC vendor Innovium.

Announced this summer, the acquisition fills a gap in the chipmaker’s lineup and positions it to compete directly with networking giant Broadcom, said Guy Azrad, SVP & GM of Marvell’s networking switch business unit, in an earlier interview. “Innovium is becoming our Tomahawk line and Prestera is our Trident line.”

Founded in 2014, Innovium has gained significant ground in the data center switching arena, raising approximately $380 million in venture funding and carving out nearly 30% of the overall merchant silicon switching market.

While Marvell didn’t announce any products specific to the Innovium acquisition, Alvares said more news would be coming in the near future. “Expect us to have more announcements on new process nodes and everything on that product plan in the near future,” he said.

Finally, in pursuit of higher performance per watt, Marvell also announced plans to offer products based on TSMC’s forthcoming 3-nanometer manufacturing process.

In addition to using TSMC’s leading-edge process technology, the chipmaker is also developing two new die-to-die interfaces to support multi-die packages for applications, like co-packaged optics.

According to Marvell, the new interfaces will enable the vendor to more efficiently package multiple dies on a single chip without sacrificing latency or power.

These technologies will enable customers to interconnect 3-nanometer and 5-nanometer dies on a single package, enabling combinations that previously weren’t possible, Alvares explained.

“Some of the technologies aren’t scaling effectively, so moving to 3 nanometer doesn’t make sense, but utilizing a multi-chip, die-to-die solution, you can utilize some 3-nanometer and some 5-nanometer to build an optimal solution,” he explained. “That’s actually what’s driving this platform announcement is the mixing and matching of technologies to optimize the total solution.”

Additionally, Marvell plans to offer chips using TSMC’s chip-on-wafer-on-substrate packaging process, which enables dies to be packaged side by side and in some cases stacked vertically.

While Marvell didn’t provide a timeline of the availability of these technologies, TSMC is slated to begin ramping production of its 3-nanometer manufacturing process in late 2022. Marvell’s products have historically trailed TSMC’s leading-edge manufacturing processes by about a year. However, according to Alvares, Marvell plans to begin shipping 3-nanometer products with the “first silicon releases” from TSMC.

Editor's Note: The original version of this story misstated the amount of funding Innovium had received prior to acquisition. We regret the error.