The Linux Foundation on Monday announced its new CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance with member companies Google, Western Digital, Esperanto Technologies, and SiFive. On the same day tech heavyweights Intel, Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise (HPE), Huawei, and Microsoft formed a consortium to develop open interconnect technology called Compute Express Link (CXL).
And both new groups formed just days before the granddaddy of open source hardware groups, Open Compute Project (OCP), holds its annual summit.
Zvonimir Bandic, senior director of next generation platforms architecture at Western Digital and a co-founder of CHIPS Alliance, says all three groups focus on different hardware elements. OCP has the broadest approach of the three, taking on open designs for complete data center products. CHIPS Alliance scope is more limited to CPU and system-on-chip (SoC) designs. And CXL is a specific interface standard.
“I do expect all the open standards organizations and all the different flavors of the open community to be very friendly to CHIPS Alliance,” he said. “It’s just a different scope, but we can all work together at the chip level.”
Jim Pappas, director of technology initiatives at Intel, said the two new groups are working on “fundamentally different areas. CHIPS Alliance and CXL are not competing standards; they are independent of each other… That said, the CXL Consortium is an open organization and encourages any silicon provider to join and contribute to the development of the specification.”
Fellow chipmaker Nvidia, which this week outbid Intel to buy Mellanox Technologies for $6.9 billion, is notably not a member of the CXL Consortium.
The foundation for the CHIPS Alliance — the open RISC-V (pronounced “risk-five”) architecture — started as a separate organization in 2016 before being handed off to the Linux Foundation. It’s an open source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. In also includes supporting software. “But it does not specify the actual implementation of a RISC-V compute, so potential architectures range from small, IoT devices to big data center processors,” Bandic said. Western Digital is also a co-founder of RISC-V. “The best analogy would be the common Linux OS for all the computers in data centers today, with every possible detail of source code known and documented.”
Under the Linux Foundation’s umbrella, companies and individuals can contribute resources to make open source CPU chip and system-on-a-chip (SoC) design more accessible to the market.
Companies producing proprietary hardware end up developing several common components in house, and then repeating that same design over and over, Bandic said. “CHIPS is looking at commonalities with RISC-V based architecture so that companies can work together on the building blocks for products,” he added. “Working with these common components and building blocks, we can have tremendous acceleration of innovation and significant cost reductions.
Western Digital will contribute its high performance, nine-stage, dual issue, 32-bit SweRV Core, together with a test bench, and high-performance SweRV instruction set simulator. It will also contribute to the specification and early implementations of the OmniXtend cache coherence protocol.
Google is also a co-founder and sits on the RISC-V board. It will contribute a Universal Verification Methodology (UVM)-based instruction stream generator environment for RISC-V cores to CHIPS Alliance. This environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner cases of designs.
“We are entering a new golden age of computer architecture highlighted by accelerators, rapid hardware development and open-source architecture and implementations,” said Amir Salek, senior director of technical infrastructure at Google Cloud in a statement. “CHIPS Alliance will provide the support and framework needed to nurture a vibrant open source hardware ecosystem for high-quality, well-verified, and documented components to accelerate and simplify chip design.”
Google’s also a founding member of the new Intel-led consortium.
“Compute Express Link is a technology that exists between the CPU and accelerator — creating a high-speed, low-latency interconnect that removes the bottlenecks in computation-intensive workloads,” Pappas wrote in an email.
Intel developed the technology behind CXL and donated it to the consortium to become the initial release of the new specification. The interconnect between the CPU and workload accelerators such as graphics processing units (GPUs) and field programmable gate arrays (FPGAs) becomes increasingly important in big-data workloads like artificial intelligence (AI) and machine learning, media, image and language processing, encryption, and cloud applications, Pappas said.
“Intel developed and donated the initial specification because our goal is to help unify and facilitate the growing accelerator ecosystem around an industry standard that is readily adoptable by the market,” he said. “We believe CXL will be a key technology in accelerating the data revolution, removing bottlenecks to unleash data’s potential and drive new market opportunities.”
The first-generation specification will be available to consortium members in the first half of 2019, Navin Shenoy, executive vice president and general manager of Intel’s Data Center Group wrote in a blog post. Intel plans to incorporate CXL technology beginning in 2021 in its data center platforms including Xeon processors, FPGAs, GPUs, and SmartNICs.