By redesigning the way it adds accelerators to a multicore processor, Freescale says it's catering more directly to software and applications developers working in software-defined networking (SDN).

Which is a fancy way to say its new Layerscape chips are meant to be easier to use. The chips aren't dumbed down; it's more that the programming is done at a higher level.

Layerscape's LS2 line, announced this week, combines a multicore CPU with a 40 Gb/s packet-processing engine and a set of accelerators for a variety of functions at Layer 3 and higher, encryption being one example. The setup steers cycle-eating functions such as packet processing and security away from the CPU, so the CPU can maintain performance.

This offloading isn't a new idea, but it usually involves directing traffic to a separate chip. (One exception is Netronome, which is targeting a higher-end market than Layerscape's.)

In programming the chip, the data plane becomes a collection of Linux objects — an abstract view in which a developer doesn't have to know details such as whether VXLAN or NVGRE was the encapsulation protocol being used.

The idea was to make the chip programmable by software people and, frankly, college recruits. Customers had found Freescale's earlier takes on this concept too difficult to program. "You kind of had to understand the hardware architecture in order to be able to use it," says Tom Deitrich, senior vice president of Freescale's digital networking group.

Layerscape's packet processing engine and accelerators are programmable in C, and Freescale is planning to offer prefab code and libraries to go with the chip.

The first two chips in the LS2 line are the 2045 and 2058, with four and eight ARM cores respectively. They're not intended to be the highest-end parts on the market. To cite a couple of arbitrary examples, Broadcom puts 20 MIPS cores on the XLP980, which officials say is shipping in "pre-production volumes." Broadcom also has its own 64-bit, ARM-based cores coming out in October.

Netronome's NFP-6000 family balances different types of cores, as Layserscape does, but is targeting higher-end performance. The chip uses the company's packet-processing and flow-processing cores, aiming for throughput of 200 Gb/s.

The CPU cores' raw performance won't outdo the best of what Intel has to offer. The goal is to use the offloading to "punch above our weight" by getting more out of those cores, says Joseph Byrne, Freescale's senior strategic marketing manager.

Layerscape isn't meant to compete at those levels, officials say. Freescale's angle is more about providing "a particular performance level within a power envelope," Deitrich says.

Like many of its competitors, Freescale is bringing the ARM processor architecture into networking. But Layerscape will also support the PowerPC processor architecture that's been Freescale's heritage. That's a nod to Freescale's installed base but it's also an acknowledgement that ARM "is still not fully institutionalized in the networking space," Deitrich says.